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? semiconductor components industries, llc, 2012 march, 2012 ? rev. p1 1 publication order number: ncp6132a/d ncp6132a, ncp6132b product preview dual output 3 phase & 2 phase controller with single svid interface for desktop and notebook cpu applications the ncp6132a/ncp6132b dual output three plus two phase buck solution is optimized for intel imvp ? 7 and vr12 compatible cpus. the controller combines true differential voltage sensing, differential inductor dcr current sensing, input voltage feed ? forward, and adaptive voltage positioning to provide accurately regulated power for both desktop and notebook applications. the control system is based on dual ? edge pulse ? width modulation (pwm) combined with dcr current sensing providing the fastest initial response to dynamic load events and reduced system cost. it also sheds to single phase during light load operation and can auto frequency scale in light load while maintaining excellent transient performance. there are three internal mosfet drivers inside the chip. one of these three integrated driver can be configured either to drive core phase or aux phase. ncp6132a and ncp6132b have almost same structure except that ncp6132a has two integrated drivers for the core rail and one integrated driver for auxiliary rail, while the ncp6132b has all three integrated drivers for the core rail. features ? meets intel?s vr12/imvp7 specifications ? three phase cpu voltage regulator, and two phase auxiliary voltage regulator, with three internal mosfet drivers in total ? current mode dual edge modulation for fastest initial response to transient loading ? dual high performance operational error amplifier ? one digital soft start ramp for both rails ? dynamic reference injection ? accurate total summing current amplifier ? dac with droop feed ? forward injection ? dual high impedance differential voltage and total current sense amplifiers ? phase ? to ? phase dynamic current balancing ? ?lossless? dcr current sensing for current balancing ? summed thermally compensated inductor current sensing for droop ? true differential current balancing sense amplifiers for each phase ? adaptive voltage positioning (avp) ? vin feed forward ramp slope ? pin programming for internal svid parameters ? over voltage protection (ovp) & under voltage protection (uvp) ? over current protection (ocp) ? dual power good output with internal delays ? pb ? free and halide ? free packages are available applications ? desktop & notebook processors this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. qfn60 case 485bb marking diagram http://onsemi.com 160 ncp6132x awlyywwg 1 x = a or b a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package device package shipping ? ordering information ncp6132amnr2g qfn60 (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. ncp6132bmnr2g
ncp6132a, ncp6132b http://onsemi.com 2 aux pwm generator main current balance data registers svid interfacce aux ovp thermal monitor uvlo & en en gnd vcc aux vr ready comparator enable enable vspa vsna daca droopa vr ready comparator enable vsp vsn dac droop vrdya vrdy tsns tsnsa vrhot# vspa vsna ovpa ovp vsp vsn ovp sdio sclk alert# enable adc vspa ? vsna vsp ? vsn tsns tsnsa imon imona imax imaxa mux vsp vsn droop dac gnd csref 1.3 v diffamp diff dac aux dac dac aux dac fb 1.3 v ? + comp error amp trbst detect trbst# ? + cs amp cssum csref cscomp iout ilim ilim iout csp1 csp2 csp3 csref core phase generator lg1 hg1 lg2 hg2 pvcc pgnd pgnd bst1 sw1 pvcc bst2 sw2 pwm drven enable comp ovp ramp generators vrmp rosc enable vspa vsna droopa gnd csrefa 1.3 v aux diffamp diffa hga bsta swa lga pgnd pvcc pwma aux current balance csp1a csp2a csrefa ramp1 ramp2 ramp3 rampa1 rampa2 aux dac + cssuma csrefa cscompa iouta ilima ilima iouta ? aux cs amp fba 1.3 v + compa ? aux error amp trbsta detect enable compa ovpa trbsta# vboot vddbp figure 1. block diagram
ncp6132a, ncp6132b http://onsemi.com 3 rosc vrmp vrdy ilim sclk vrhot# sdio alert# fba trbst# vcc sw1 hg1 diffa compa cssuma csrefa csp2a cscompa ilima pwm bst1 csp1a vsna vddbp vspa drven vsp csp1 csref cscomp csp2 droopa iout bsta pvcc hga swa lga bst2 hg2 sw2 lg2 comp cssum pgnd vsn fb lg1 csp3 vboot pwma diff en tab: gnd iouta vrdya 1 60 15 16 46 45 31 30 ncp6132a/ncp6132b droop tsnsa tsns trbsta# figure 2. qfn60 pin diagram table 1. qfn60 pin list description pin no. symbol description 1 vcc power for the internal control circuits. a decoupling capacitor is connected from this pin to ground. 2 vddbp digital logic power. connect this pin to vcc with 10 . connect 0.1 f capacitor from this pin to ground 3 vrdya open drain output. high indicates that the aux output is regulating. 4 en logic input. logic high enables both outputs and logic low disables both outputs. 5 sdio serial vid data interface. 6 alert# serial vid alert#. 7 sclk serial vid clock. 8 vboot a resistor to gnd on this pin sets the core and aux boot ? up voltage 9 rosc a resistance from this pin to ground programs the oscillator frequency. this pin supplies a trimmed output voltage of 2 v. 10 vrmp feed ? forward input of vin for the ramp slope compensation. the current fed into this pin is used to control of the ramp of pwm slope 11 vrhot# thermal logic output for over temperature. 12 vrdy open drain output. high indicates that the core output is regulating. 13 vsn inverting input to the core differential remote sense amplifier. 14 vsp non ? inverting input to the core differential remote sense amplifier. 15 diff output of the core differential remote sense amplifier. 16 trbst# compensation pin for the load transient boost. 17 fb error amplifier voltage feedback for core output 18 comp output of the error amplifier and the inverting inputs of the pwm comparators for the core output. 19 iout total output current monitor for core output. short it to gnd if imon function is not needed. 20 ilim over current shutdown threshold setting for core output. resistor to cscomp to set threshold. 21 droop used to program droop function for core output. it?s connected to the resistor divider placed between cscomp and csref summing node. 22 cscomp output of total current sense amplifier for core output.
ncp6132a, ncp6132b http://onsemi.com 4 table 1. qfn60 pin list description pin no. description symbol 23 cssum inverting input of total current sense amplifier for core output. 24 csref total output current sense amplifier reference voltage input. and inverting input to core current bal- ance sense amplifiers. 25 csp3 non ? inverting input to current balance sense amplifier for phase 3 26 csp2 non ? inverting input to current balance sense amplifier for phase 2 27 csp1 non ? inverting input to current balance sense amplifier for phase 1 28 tsns temp sense input for the core converter. 29 drven bidirectional gate driver enable for external drivers for both core and aux rails. it should be left floating if unused. 30 pwm phase 3 pwm output. a resistor to ground on this pin programs imax. 31 bst1 high ? side bootstrap supply for phase 1 32 hg1 high ? side gate drive output for phase 1 33 sw1 current return for high ? side gate drive for phase 1 34 lg1 low ? side gate drive output for phase 1 35 pgnd power ground for gate drivers 36 pvcc power supply for gate drivers 37 lg2 low ? side gate drive output for phase 2 38 sw2 current return for high ? side gate drive for phase 2 39 hg2 high ? side gate drive output for phase 2 40 bst2 high ? side bootstrap supply for phase 2 41 lga low ? side gate drive output for aux phase 1 42 swa current return for high ? side gate drive for aux phase 1 43 hga high ? side gate drive output for aux phase 1 44 bsta high ? side bootstrap supply for aux phase 1 45 pwma aux phase 2 pwm output. a resistor to ground on this pin programs imaxa. 46 tsnsa temp sense for the aux converter 47 csp1a non ? inverting input to aux current balance sense amplifier for phase 1 48 csp2a non ? inverting input to aux current balance sense amplifier for phase 2 49 csrefa total output current sense amplifier reference voltage input for aux. inverting input to aux current balance sense amplifier for phase 1 and 2 50 cssuma inverting input of total current sense amplifier for aux output 51 cscompa output of total current sense amplifier for aux output 52 droopa used to program droop function for aux output. it?s connected to the resistor divider placed between cscompa and csrefa. 53 ilma over current shutdown threshold setting for aux output. resistor to cscompa to set threshold. 54 iouta total output current monitor for aux output. short to gnd if imon function is not needed. 55 compa output of aux error amplifier and inverting input of pwm comparator for aux output 56 fba error amplifier voltage feedback for aux output 57 trbsta# compensation pin for load transient boost 58 diffa output of the aux differential remote sense amplifier 59 vspa non ? inverting input to aux differential remote sense amplifier 60 vsna inverting input to aux differential remote sense amplifier 61 gnd analog ground
ncp6132a, ncp6132b http://onsemi.com 5 absolute maximum ratings table 2. electrical information pin symbol v max v min i source i sink comp, compa v cc + 0.3 v ? 0.3 v 2 ma 2 ma cscomp, cscompa v cc + 0.3 v ? 0.3 v 2 ma 2 ma vsn, vsna gnd + 300 mv gnd ? 300 mv 1 ma 1 ma diff, diffa v cc + 0.3 v ? 0.3 v 2 ma 2 ma vrdy, vrdya v cc + 0.3 v ? 0.3 v n/a 2 ma vddpb, vcc, pvcc 6.5 v ? 0.3 v n/a n/a rosc v cc + 0.3 v ? 0.3 v 1 ma n/a iout, iouta output tbd ? 0.3 v vrmp +25 v ? 0.3 v sw1, sw2, swa 28 v ? 5 v ? 10 v 200 ns bst1, bst2, bsta 34 v wrt/ gnd 6.5 v wrt/ sw ? 0.3 v wrt/ sw lg1, lg2, lga v cc + 0.3 v ? 0.3 v ? 5 v 200 ns hg1, hg2, hga bst + 0.3 v ? 0.3 v wrt/ sw ? 2 v 200 ns wrt/ sw all other pins v cc + 0.3 v ? 0.3 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *all signals referenced to gnd unless noted otherwise. table 3. thermal information parameters symbol typical units thermal characteristic qfn package (note 1) r ja 31 c/w operating junction temperature range (note 2) t j ? 10 to +125 c operating ambient temperature range ? 10 to +100 c maximum storage temperature range t stg ? 40 to +150 c moisture sensitivity level qfn package msl 1 *the maximum package power dissipation must be observed. 1. jesd 51 ? 5 (1s2p direct ? attach method) with 0 lfm 2. jesd 51 ? 7 (1s2p direct ? attach method) with 0 lfm
ncp6132a, ncp6132b http://onsemi.com 6 table 4. ncp6132a/ncp6132b (3+2) electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5.0 v; c vcc = 0.1 f parameter test conditions min typ max units error amplifier input bias current ? 400 400 na open loop dc gain cl = 20 pf to gnd, rl = 10 k to gnd 80 db open loop unity gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd 55 mhz slew rate v in = 100 mv, g = ? 10 v/v, v out = 1.5 v ? 2.5 v, c l = 20 pf to gnd, dc load = 10k to gnd 20 v/ s maximum output voltage i source = 2.0 ma 3.5 ? ? v minimum output voltage i sink = 2.0 ma ? ? 1 v differential summing amplifier input bias current ? 400 ? 400 na vsp input voltage range ? 0.3 ? 3.0 v vsn input voltage range ? 0.3 ? 0.3 v ? 3 db bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 12 mhz closed loop dc gain vs to diff vs+ to vs ? = 0.5 to 1.3 v 1.0 v/v droop accuracy csref ? droop = 80 mv dac = 0.8 v to 1.2 v ? 10 c ~ 100 c ? 10 c ~ 85 c 78.5 79 81.5 81 mv maximum output voltage i source = 2 ma 3.0 ? ? v minimum output voltage i sink = 2 ma ? ? 0.5 v 3. guaranteed by design/characterization, not in production test 4. guaranteed by characterization
ncp6132a, ncp6132b http://onsemi.com 7 table 5. electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5.0 v; c vcc = 0.1 f parameter test conditions min typ max units current summing amplifier offset voltage (vos) ? 300 300 v input bias current (cssum) cssum = csref = 1 v ? 7.5 7.5 na open loop gain 80 db current sense unity gain bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 10 mhz maximum cscomp (a) output voltage i source = 2 ma 3.5 ? ? v minimum cscomp(a) output voltage i sink = 500 a ? ? 0.1 v current balance amplifier input bias current cspx = csref = 1.2 v ? 50 ? 50 na common mode input voltage range cspx = csref 0 ? 2.0 v differential mode input voltage range csref = 1.2 v ? 100 ? 100 mv input offset voltage matching cspx = csref = 1.2 v, measured from the average ? 1.5 ? 1.5 mv current sense amplifier gain 0 v < cspx ? csref < 0.1 v, ? 10 c ~ 85 c ? 10 c ~ 100 c 5.7 5.5 6.0 6.0 6.3 6.3 v/v multiphase current sense gain matching csref = csp = 10 mv to 30 mv ? 3 3 % ? 3 db bandwidth 8 mhz bias supply v cc quiescent current en = high 20 27 35 ma en = low 10 70 a uvlo threshold v cc rising 4.5 v v cc falling 4.0 v vcc uvlo hysteresis 200 mv vddbp quiescent current en = low en = high 0.8 12.0 ma dac slew rate soft start slew rate 2.33 mv/ s slew rate slow 3.5 mv/ s slew rate fast 13.5 mv/ s aux soft start slew rate 2.33 mv/ s aux slew rate slow 3.5 mv/ s aux slew rate fast 13.5 mv/ s enable input enable high input leakage current external 1k pull ? up to 3.3 v ? 1.0 a upper threshold v upper 0.8 v lower threshold v lower 0.35 v total hysteresis v upper ? v lower 95 mv enable delay time measure time from enable transitioning hi to when dron goes high, v boot is not 0 v 5.0 ms 3. guaranteed by design/characterization, not in production test 4. guaranteed by characterization
ncp6132a, ncp6132b http://onsemi.com 8 table 5. electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5.0 v; c vcc = 0.1 f parameter units max typ min test conditions drven output high voltage sourcing 500 a 3.5 v output low voltage sinking 500 a 0.1 v rise time cl (pcb) = 20 pf, vo = 10% to 90% ? 255 ? ns fall time ? 2 ? ns internal pull down resistance en = low 70 k iout / iouta output maximum output voltage r lim = 5k 2.5 v input referred offset voltage i limit to csref ? 2.5 2.5 mv output source current i limit sink current = 80 a 840 a current gain (iout current ) / (ilim current ), r ilim = r out = 8.0 k , temp range: 0 c to 60 c 9.5 10 10.5 oscillator switching frequency range 200 ? 800 khz switching frequency accuracy 200 khz < f sw < 800 khz ? 10 ? 10 % 3 phase operation r osc = 67.4 k 360 400 440 khz rosc output voltage r osc = 67.4 k 1.95 2.00 2.05 v output over voltage & under voltage protection (ovp & uvp) over voltage threshold during soft ? start & dvid 1.7 1.75 1.8 v over voltage threshold above dac vsp(a) rising 225 250 275 mv over voltage delay vsp(a) rising to pwmx low 50 ns under voltage threshold below dac ? droop vsp(a) falling 350 400 450 mv under ? voltage hysteresis vsp(a) rising 25 mv under ? voltage delay 5 s vr12 dac system voltage accuracy ? 10 c ~ 85 c 1.0 v dac < 1.52 v 0.8 v< dac < 0.995 v 0.5 v < dac < 0.795 v 0.25 v < dac < 0.495 v ? 10 c ~ 100 c 1.0 v dac < 1.52 v 0.8 v< dac < 0.995 v 0.5 v < dac < 0.795 v 0.25 v < dac < 0.495 v ? 0.5 ? 5 ? 8 ? 8 1 ? 12 ? 12 ? 12 +0.5 +5 +8 +8 1 +12 +12 +12 % mv mv mv % mv mv mv droop feed ? forward current measure on droop pin 60 66 72 a droop feed ? forward pulse on ? time 0.16 s overcurrent protection ilim threshold current (ocp shutdown after 50 s delay) aux/core multiphase, ps0, r lim = 20 k 9.0 10 11.0 a aux/core 1 ? phase, ps1/2/3, r lim = 20 k 10 a aux 2 ? phase, ps1, r lim = 20 k 10 a core 2 ? phase, ps1, r lim = 20 k 6.5 a aux/core 2 ? phase, ps2/3, r lim = 20 k 6.5 a core 3 ? phase, ps1/2/3, r lim = 20 k 4.0 a 3. guaranteed by design/characterization, not in production test 4. guaranteed by characterization
ncp6132a, ncp6132b http://onsemi.com 9 table 5. electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5.0 v; c vcc = 0.1 f parameter units max typ min test conditions overcurrent protection ilim threshold current (immediate ocp shutdown) aux/core multiphase, ps0, r lim = 20 k 13.5 15 16.5 a aux/core 1 ? phase, ps1/2/3, r lim = 20 k 15 a aux 2 ? phase, ps1, r lim = 20 k 15 a core 2 ? phase, ps1, r lim = 20 k 10 a aux/core 2 ? phase, ps2/3, r lim = 20 k 10 a core 3 ? phase, ps1/2/3, r lim = 20 k 6 a modulators (pwm comparators) for core & aux minimum pulse width f sw = 350 khz 60 ns 0% duty cycle comp voltage when the pwm outputs remain lo 1.3 ? v 100% duty cycle comp voltage when the pwm outputs remain hi v rmp = 12.0 v ? 2.5 ? v pwm ramp duty cycle matching comp = 2 v, pwm ton matching ? 20 20 % pwm phase angle error between adjacent phases ? 25 25 deg ramp feed ? forward voltage range 5 22 v trbst# trbst/comp offset trbst starts sinking current 350 mv trbst sink capability 500 a trbsta# trbsta/compa offset trbsta starts sinking current 350 mv trbsta sink capability 500 a vrhot# output low voltage i_ vrhot = ? 4 ma 0.3 v output leakage current high impedance state ? 1.0 ? 1.0 a tsns/tsnsa alert# assert threshold 515 mv alert# de ? assert threshold 533 mv vrhot# assert threshold 496 mv vrhot# rising threshold 515 mv tsns bias current 115 120 125 a adc voltage range 0 2 v total unadjusted error (tue) ? 1 +1 % differential nonlinearity (dnl) 8 ? bit 1 lsb power supply sensitivity +/ ? 1 % conversion time 30 s round robin 90 s vrdy, vrdya (power good) output output low saturation voltage i vrdy(a) = 4 ma ? ? 0.3 v 3. guaranteed by design/characterization, not in production test 4. guaranteed by characterization
ncp6132a, ncp6132b http://onsemi.com 10 table 5. electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5.0 v; c vcc = 0.1 f parameter units max typ min test conditions vrdy, vrdya (power good) output rise time external pull ? up of 1 k to 3.3 v, c tot = 45 pf, vo = 10% to 90% ? 100 ns fall time external pull ? up of 1 k to 3.3 v, c tot = 45 pf, vo = 90% to 10% 10 ns output voltage at power ? up vrdy, vrdya pulled up to 5 v via 2 k ? ? 1.0 v output leakage current when high vrdy & vrdya = 5.0 v ? 1.0 ? 1.0 a vrdy delay (rising) dac = target to vrdy 500 s vrdy delay (falling) from ocp or ovp ? 5 ? s pwm, pwma outputs output high voltage sourcing 500 a v cc ? 1.0 v ? ? v output mid voltage no load, setps = 02 1.3 2.0 2.7 v output low voltage sinking 500 a ? ? 0.7 v rise and fall time cl (pcb) = 50 pf, vo = gnd to vcc ? 10 ns tri ? state output leakage gx = 2.0 v, x = 1 ? 4, en = low ? 1.0 ? 1.0 a phase detection csp1a, csp2a, csp2, csp3 pin threshold voltage 4.2 v sclk, sdio v il input low voltage 0.45 v v ih input high voltage 0.65 v v hys hysteresis voltage 50 mv v oh output high voltage 1.05 v v ol output low voltage (sdio only) tbd mv r on buffer on resistance (data line, alert#, and vrhot#) 4 13 leakage current ? 100 100 a pad capacitance (note 3) 4.0 pf vr clock to data delay (tco) (note 3) 4 8.3 ns setup time (tsu) (note 3) 7 ns hold time (thld) (note 3) 14 ns high ? side mosfet driver pull ? up resistance, sourcing current (note 4) bst = pvcc 1.2 2.0 high side driver sourcing current bst = pvcc 4.17 a pull ? down resistance, sinking current (note 4) bst = pvcc 0.8 2.0 high side driver sinking current bst = pvcc 6.25 a hg1, hg2, hga rise time v cc = 5 v, 3 nf load, bst ? sw = 5 v 6 16 30 ns hg1, hg2, hga fall time v cc = 5 v, 3 nf load, bst ? sw = 5 v 6 11 30 ns hg1, hg2, hga turn ? on propagation delay tpdh drvh c load = 3 nf 16 40 47 ns sw1, sw2, swa pull ? down resistance sw to pgnd 2 k 3. guaranteed by design/characterization, not in production test 4. guaranteed by characterization
ncp6132a, ncp6132b http://onsemi.com 11 table 5. electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5.0 v; c vcc = 0.1 f parameter units max typ min test conditions high ? side mosfet driver hg1, hg2, hga pull ? down resistance hg to swbst ? sw = 0 v 260 k bst quiescent current en = l (shutdown) en = h, no switching 1.0 300 10 a low ? side mosfet driver pull ? up resistance, sourcing current (note 4) 0.9 2.0 low side driver sourcing current 5.56 a pull ? down resistance, sinking current (note 4) 0.4 1.0 low side driver sinking current 12.5 a lg1, lg2, lga rise time 3 nf load 6 16 30 ns lg1, lg2, lga fall time 3 nf load 6 11 30 ns lg1, lg2, lga turn ? on propagation delay tpdh drvl c load = 3 nf 11 30 ns lg1, lg2, lga pull ? down resistance lg to pgnd, v cc = 5 v 45 k pvcc quiescent current en = l (shutdown) en = h, no switching 1.0 490 10 a bootstrap rectifier switch on resistance en = l or en = h and drvl = h 5.0 9.0 14.0 3. guaranteed by design/characterization, not in production test 4. guaranteed by characterization v th v th 1.0v tpdh drvh tpdh drvl tr drvh tf drvh tr drvl drvl drvh (with respect to sw) sw tf drvl figure 3. timing diagram note: timing is referenced to the 90% and 10% points, unless otherwise noted.
ncp6132a, ncp6132b http://onsemi.com 12 table 6. vr12, imvp ? 7 vid codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage (v) hex 0 0 0 0 0 0 0 0 off 00 0 0 0 0 0 0 0 1 0.25000 01 0 0 0 0 0 0 1 0 0.25500 02 0 0 0 0 0 0 1 1 0.26000 03 0 0 0 0 0 1 0 0 0.26500 04 0 0 0 0 0 1 0 1 0.27000 05 0 0 0 0 0 1 1 0 0.27500 06 0 0 0 0 0 1 1 1 0.28000 07 0 0 0 0 1 0 0 0 0.28500 08 0 0 0 0 1 0 0 1 0.29000 09 0 0 0 0 1 0 1 0 0.29500 0a 0 0 0 0 1 0 1 1 0.30000 0b 0 0 0 0 1 1 0 0 0.30500 0c 0 0 0 0 1 1 0 1 0.31000 0d 0 0 0 0 1 1 1 0 0.31500 0e 0 0 0 0 1 1 1 1 0.32000 0f 0 0 0 1 0 0 0 0 0.32500 10 0 0 0 1 0 0 0 1 0.33000 11 0 0 0 1 0 0 1 0 0.33500 12 0 0 0 1 0 0 1 1 0.34000 13 0 0 0 1 0 1 0 0 0.34500 14 0 0 0 1 0 1 0 1 0.35000 15 0 0 0 1 0 1 1 0 0.35500 16 0 0 0 1 0 1 1 1 0.36000 17 0 0 0 1 1 0 0 0 0.36500 18 0 0 0 1 1 0 0 1 0.37000 19 0 0 0 1 1 0 1 0 0.37500 1a 0 0 0 1 1 0 1 1 0.38000 1b 0 0 0 1 1 1 0 0 0.38500 1c 0 0 0 1 1 1 0 1 0.39000 1d 0 0 0 1 1 1 1 0 0.39500 1e 0 0 0 1 1 1 1 1 0.40000 1f 0 0 1 0 0 0 0 0 0.40500 20 0 0 1 0 0 0 0 1 0.41000 21 0 0 1 0 0 0 1 0 0.41500 22 0 0 1 0 0 0 1 1 0.42000 23 0 0 1 0 0 1 0 0 0.42500 24 0 0 1 0 0 1 0 1 0.43000 25 0 0 1 0 0 1 1 0 0.43500 26 0 0 1 0 0 1 1 1 0.44000 27 0 0 1 0 1 0 0 0 0.44500 28 0 0 1 0 1 0 0 1 0.45000 29 0 0 1 0 1 0 1 0 0.45500 2a
ncp6132a, ncp6132b http://onsemi.com 13 table 6. vr12, imvp ? 7 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 0 1 0 1 0 1 1 0.46000 2b 0 0 1 0 1 1 0 0 0.46500 2c 0 0 1 0 1 1 0 1 0.47000 2d 0 0 1 0 1 1 1 0 0.47500 2e 0 0 1 0 1 1 1 1 0.48000 2f 0 0 1 1 0 0 0 0 0.48500 30 0 0 1 1 0 0 0 1 0.49000 31 0 0 1 1 0 0 1 0 0.49500 32 0 0 1 1 0 0 1 1 0.50000 33 0 0 1 1 0 1 0 0 0.50500 34 0 0 1 1 0 1 0 1 0.51000 35 0 0 1 1 0 1 1 0 0.51500 36 0 0 1 1 0 1 1 1 0.52000 37 0 0 1 1 1 0 0 0 0.52500 38 0 0 1 1 1 0 0 1 0.53000 39 0 0 1 1 1 0 1 0 0.53500 3a 0 0 1 1 1 0 1 1 0.54000 3b 0 0 1 1 1 1 0 0 0.54500 3c 0 0 1 1 1 1 0 1 0.55000 3d 0 0 1 1 1 1 1 0 0.55500 3e 0 0 1 1 1 1 1 1 0.56000 3f 0 1 0 0 0 0 0 0 0.56500 40 0 1 0 0 0 0 0 1 0.57000 41 0 1 0 0 0 0 1 0 0.57500 42 0 1 0 0 0 0 1 1 0.58000 43 0 1 0 0 0 1 0 0 0.58500 44 0 1 0 0 0 1 0 1 0.59000 45 0 1 0 0 0 1 1 0 0.59500 46 0 1 0 0 0 1 1 1 0.60000 47 0 1 0 0 1 0 0 0 0.60500 48 0 1 0 0 1 0 0 1 0.61000 49 0 1 0 0 1 0 1 0 0.61500 4a 0 1 0 0 1 0 1 1 0.62000 4b 0 1 0 0 1 1 0 0 0.62500 4c 0 1 0 0 1 1 0 1 0.63000 4d 0 1 0 0 1 1 1 0 0.63500 4e 0 1 0 0 1 1 1 1 0.64000 4f 0 1 0 1 0 0 0 0 0.64500 50 0 1 0 1 0 0 0 1 0.65000 51 0 1 0 1 0 0 1 0 0.65500 52 0 1 0 1 0 0 1 1 0.66000 53 0 1 0 1 0 1 0 0 0.66500 54 0 1 0 1 0 1 0 1 0.67000 55
ncp6132a, ncp6132b http://onsemi.com 14 table 6. vr12, imvp ? 7 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 1 0 1 0 1 1 0 0.67500 56 0 1 0 1 0 1 1 1 0.68000 57 0 1 0 1 1 0 0 0 0.68500 58 0 1 0 1 1 0 0 1 0.69000 59 0 1 0 1 1 0 1 0 0.69500 5a 0 1 0 1 1 0 1 1 0.70000 5b 0 1 0 1 1 1 0 0 0.70500 5c 0 1 0 1 1 1 0 1 0.71000 5d 0 1 0 1 1 1 1 0 0.71500 5e 0 1 0 1 1 1 1 1 0.72000 5f 0 1 1 0 0 0 0 0 0.72500 60 0 1 1 0 0 0 0 1 0.73000 61 0 1 1 0 0 0 1 0 0.73500 62 0 1 1 0 0 0 1 1 0.74000 63 0 1 1 0 0 1 0 0 0.74500 64 0 1 1 0 0 1 0 1 0.75000 65 0 1 1 0 0 1 1 0 0.75500 66 0 1 1 0 0 1 1 1 0.76000 67 0 1 1 0 1 0 0 0 0.76500 68 0 1 1 0 1 0 0 1 0.77000 69 0 1 1 0 1 0 1 0 0.77500 6a 0 1 1 0 1 0 1 1 0.78000 6b 0 1 1 0 1 1 0 0 0.78500 6c 0 1 1 0 1 1 0 1 0.79000 6d 0 1 1 0 1 1 1 0 0.79500 6e 0 1 1 0 1 1 1 1 0.80000 6f 0 1 1 1 0 0 0 0 0.80500 70 0 1 1 1 0 0 0 1 0.81000 71 0 1 1 1 0 0 1 0 0.81500 72 0 1 1 1 0 0 1 1 0.82000 73 0 1 1 1 0 1 0 0 0.82500 74 0 1 1 1 0 1 0 1 0.83000 75 0 1 1 1 0 1 1 0 0.83500 76 0 1 1 1 0 1 1 1 0.84000 77 0 1 1 1 1 0 0 0 0.84500 78 0 1 1 1 1 0 0 1 0.85000 79 0 1 1 1 1 0 1 0 0.85500 7a 0 1 1 1 1 0 1 1 0.86000 7b 0 1 1 1 1 1 0 0 0.86500 7c 0 1 1 1 1 1 0 1 0.87000 7d 0 1 1 1 1 1 1 0 0.87500 7e 0 1 1 1 1 1 1 1 0.88000 7f 1 0 0 0 0 0 0 0 0.88500 80
ncp6132a, ncp6132b http://onsemi.com 15 table 6. vr12, imvp ? 7 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 0 0 0 0 0 0 1 0.89000 81 1 0 0 0 0 0 1 0 0.89500 82 1 0 0 0 0 0 1 1 0.90000 83 1 0 0 0 0 1 0 0 0.90500 84 1 0 0 0 0 1 0 1 0.91000 85 1 0 0 0 0 1 1 0 0.91500 86 1 0 0 0 0 1 1 1 0.92000 87 1 0 0 0 1 0 0 0 0.92500 88 1 0 0 0 1 0 0 1 0.93000 89 1 0 0 0 1 0 1 0 0.93500 8a 1 0 0 0 1 0 1 1 0.94000 8b 1 0 0 0 1 1 0 0 0.94500 8c 1 0 0 0 1 1 0 1 0.95000 8d 1 0 0 0 1 1 1 0 0.95500 8e 1 0 0 0 1 1 1 1 0.96000 8f 1 0 0 1 0 0 0 0 0.96500 90 1 0 0 1 0 0 0 1 0.97000 91 1 0 0 1 0 0 1 0 0.97500 92 1 0 0 1 0 0 1 1 0.98000 93 1 0 0 1 0 1 0 0 0.98500 94 1 0 0 1 0 1 0 1 0.99000 95 1 0 0 1 0 1 1 0 0.99500 96 1 0 0 1 0 1 1 1 1.00000 97 1 0 0 1 1 0 0 0 1.00500 98 1 0 0 1 1 0 0 1 1.01000 99 1 0 0 1 1 0 1 0 1.01500 9a 1 0 0 1 1 0 1 1 1.02000 9b 1 0 0 1 1 1 0 0 1.02500 9c 1 0 0 1 1 1 0 1 1.03000 9d 1 0 0 1 1 1 1 0 1.03500 9e 1 0 0 1 1 1 1 1 1.04000 9f 1 0 1 0 0 0 0 0 1.04500 a0 1 0 1 0 0 0 0 1 1.05000 a1 1 0 1 0 0 0 1 0 1.05500 a2 1 0 1 0 0 0 1 1 1.06000 a3 1 0 1 0 0 1 0 0 1.06500 a4 1 0 1 0 0 1 0 1 1.07000 a5 1 0 1 0 0 1 1 0 1.07500 a6 1 0 1 0 0 1 1 1 1.08000 a7 1 0 1 0 1 0 0 0 1.08500 a8 1 0 1 0 1 0 0 1 1.09000 a9 1 0 1 0 1 0 1 0 1.09500 aa 1 0 1 0 1 0 1 1 1.10000 ab
ncp6132a, ncp6132b http://onsemi.com 16 table 6. vr12, imvp ? 7 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 0 1 0 1 1 0 0 1.10500 ac 1 0 1 0 1 1 0 1 1.11000 ad 1 0 1 0 1 1 1 0 1.11500 ae 1 0 1 0 1 1 1 1 1.12000 af 1 0 1 1 0 0 0 0 1.12500 b0 1 0 1 1 0 0 0 1 1.13000 b1 1 0 1 1 0 0 1 0 1.13500 b2 1 0 1 1 0 0 1 1 1.14000 b3 1 0 1 1 0 1 0 0 1.14500 b4 1 0 1 1 0 1 0 1 1.15000 b5 1 0 1 1 0 1 1 0 1.15500 b6 1 0 1 1 0 1 1 1 1.16000 b7 1 0 1 1 1 0 0 0 1.16500 b8 1 0 1 1 1 0 0 1 1.17000 b9 1 0 1 1 1 0 1 0 1.17500 ba 1 0 1 1 1 0 1 1 1.18000 bb 1 0 1 1 1 1 0 0 1.18500 bc 1 0 1 1 1 1 0 1 1.19000 bd 1 0 1 1 1 1 1 0 1.19500 be 1 0 1 1 1 1 1 1 1.20000 bf 1 1 0 0 0 0 0 0 1.20500 c0 1 1 0 0 0 0 0 1 1.21000 c1 1 1 0 0 0 0 1 0 1.21500 c2 1 1 0 0 0 0 1 1 1.22000 c3 1 1 0 0 0 1 0 0 1.22500 c4 1 1 0 0 0 1 0 1 1.23000 c5 1 1 0 0 0 1 1 0 1.23500 c6 1 1 0 0 0 1 1 1 1.24000 c7 1 1 0 0 1 0 0 0 1.24500 c8 1 1 0 0 1 0 0 1 1.25000 c9 1 1 0 0 1 0 1 0 1.25500 ca 1 1 0 0 1 0 1 1 1.26000 cb 1 1 0 0 1 1 0 0 1.26500 cc 1 1 0 0 1 1 0 1 1.27000 cd 1 1 0 0 1 1 1 0 1.27500 ce 1 1 0 0 1 1 1 1 1.28000 cf 1 1 0 1 0 0 0 0 1.28500 d0 1 1 0 1 0 0 0 1 1.29000 d1 1 1 0 1 0 0 1 0 1.29500 d2 1 1 0 1 0 0 1 1 1.30000 d3 1 1 0 1 0 1 0 0 1.30500 d4 1 1 0 1 0 1 0 1 1.31000 d5 1 1 0 1 0 1 1 0 1.31500 d6
ncp6132a, ncp6132b http://onsemi.com 17 table 6. vr12, imvp ? 7 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 1 0 1 0 1 1 1 1.32000 d7 1 1 0 1 1 0 0 0 1.32500 d8 1 1 0 1 1 0 0 1 1.33000 d9 1 1 0 1 1 0 1 0 1.33500 da 1 1 0 1 1 0 1 1 1.34000 db 1 1 0 1 1 1 0 0 1.34500 dc 1 1 0 1 1 1 0 1 1.35000 dd 1 1 0 1 1 1 1 0 1.35500 de 1 1 0 1 1 1 1 1 1.36000 df 1 1 1 0 0 0 0 0 1.36500 e0 1 1 1 0 0 0 0 1 1.37000 e1 1 1 1 0 0 0 1 0 1.37500 e2 1 1 1 0 0 0 1 1 1.38000 e3 1 1 1 0 0 1 0 0 1.38500 e4 1 1 1 0 0 1 0 1 1.39000 e5 1 1 1 0 0 1 1 0 1.39500 e6 1 1 1 0 0 1 1 1 1.40000 e7 1 1 1 0 1 0 0 0 1.40500 e8 1 1 1 0 1 0 0 1 1.41000 e9 1 1 1 0 1 0 1 0 1.41500 ea 1 1 1 0 1 0 1 1 1.42000 eb 1 1 1 0 1 1 0 0 1.42500 ec 1 1 1 0 1 1 0 1 1.43000 ed 1 1 1 0 1 1 1 0 1.43500 ee 1 1 1 0 1 1 1 1 1.44000 ef 1 1 1 1 0 0 0 0 1.44500 f0 1 1 1 1 0 0 0 1 1.45000 f1 1 1 1 1 0 0 1 0 1.45500 f2 1 1 1 1 0 0 1 1 1.46000 f3 1 1 1 1 0 1 0 0 1.46500 f4 1 1 1 1 0 1 0 1 1.47000 f5 1 1 1 1 0 1 1 0 1.47500 f6 1 1 1 1 0 1 1 1 1.48000 f7 1 1 1 1 1 0 0 0 1.48500 f8 1 1 1 1 1 0 0 1 1.49000 f9 1 1 1 1 1 0 1 0 1.49500 fa 1 1 1 1 1 0 1 1 1.50000 fb 1 1 1 1 1 1 0 0 1.50500 fc 1 1 1 1 1 1 0 1 1.51000 fd 1 1 1 1 1 1 1 0 1.51500 fe 1 1 1 1 1 1 1 1 1.52000 ff
ncp6132a, ncp6132b http://onsemi.com 18 en sclk sdio vspa vid pkt vspa svid bus idle vsp vid pkt vsp svid alert vrdya vrdy status pkt 12v 5v figure 4. start up timing diagram sclk sdio t co _cpu t su t hld t co _cpu vr latch cpu send t co_cpu = clock to data delay in cpu tsu =0.5*t ? t co_cpu thld =0.5*t +t co_cpu cpu driving, single data rate sclk sdio t co _vr t su t hld cpu latch vr send t co_vr = clock to data delay in vr tsu =t ? 2*t fly ? t co_vr thld =2*t fly + t co_vr t fly propagation time on serial vid bus vr driving, single data rate figure 5. svid timing diagram
ncp6132a, ncp6132b http://onsemi.com 19 table 7. state truth table state vrdy(a) pin error amp comp(a) pin ovp(a) & uvp(a) drven pin method of reset por 0 < v cc < uvlo n/a n/a n/a resistive pull down disabled en < threshold uvlo > threshold low low disabled low start up delay & calibration en > threshold uvlo > threshold low low disabled low drven fault en > threshold uvlo > threshold drven < threshold low low disabled resistive pull up driver must release drven to high soft start en > threshold uvlo > threshold drven > high low operational active / no latch high normal operation en > threshold uvlo > threshold drven > high high operational active / latching high n/a over voltage low n/a dac + 150 mv high over current low operational last dac code low vid code = 00h follows the multivr config register (34h) bit 0 setting low disabled high, pwm/pwma outputs in low state lgx outputs in high state set valid vid code
ncp6132a, ncp6132b http://onsemi.com 20 controller por disable vcc > uvlo calibrate drive off phase detect soft start ramp normal vrdy ovp uvp en = 1 3 . 5 ms and cal done vccp > uvlo and dron high en = 0 vs > ovp vdrp > ilim no _ cpu invalid vid vs < uvp vs > uvp dac = vid vcc < uvlo soft start ramp dac = vboot figure 6. state diagram
ncp6132a, ncp6132b http://onsemi.com 21 general the ncp6132a/ncp6132b is a dual output three phase plus two phase dual edge modulated multiphase pwm controller designed to meet the intel vr12 and imvp ? 7 specifications with a serial svid control interface. it is designed to work in notebook, desktop, and server applications. user ? set phase and driver selection ncp6132a/ncp6132b can be user ? configured to operate under different phase and driver combinations. phase selection for core and aux regulator can be set up separately by configuring the pin connections of csp2, csp3, csp1a, and csp2a. during start ? up (before svid is available), cspx pins are monitored to detect user ? set configuration. if a pin is connected to vcc directly or through a low value (1 k ) resistor, the monitored input signal is driven to logic high indicating that the corresponding phase is disabled. otherwise, if a pin is connected normally, the monitored input signal is driven to logic low and that phase is operational. during initialization, the configuration defined by cspx is written into a user configuration register (ucr). if the detected configuration doesn?t match any of the valid configurations listed in the table below then it is considered as unsupported. with an unsupported configuration the chip doesn?t start switching but remains power ? up. after initialization the ucr acts as a read ? only reg. the user configuration for core and aux regulator is shown as below: no core rail aux rail csp2 csp3 csp1a csp2a part 1 2 int. + 1 ext. 1 int. + 1 ext. normal normal normal normal ncp6132a 2 2 int. + 1 ext. 1 int. normal normal normal vcc ncp6132a 3 2 int. + 1 ext. off normal normal vcc vcc ncp6132a 4 3 int. 2 ext. normal normal normal normal ncp6132b 5 3 int. 1 ext. normal normal normal vcc ncp6132b 6 3 int. off normal normal vcc vcc ncp6132b 7 2 int. 1 int. + 1 ext. normal vcc normal normal ncp6132a 8 2 int. 1 int. normal vcc normal vcc ncp6132a 9 2 int. 2 ext. normal vcc normal normal ncp6132b 10 2 int. 1 ext. normal vcc normal vcc ncp6132b 11 2 int. off normal vcc vcc vcc ncp6132a or ncp6132b 12 1 int. 1 int. vcc vcc normal vcc ncp6132a 13 1 int. 1 ext. vcc vcc normal vcc ncp6132b 14 1 int. off vcc vcc vcc vcc ncp6132a or ncp6132b *ncp6132a supports configurations: 1, 2, 3, 7, 8, 11, 12 and 14; ncp6132b supports configurations: 4, 5, 6, 9, 10, 11, 13, 14. *when both csp1a and csp2a are pulled to v cc , the aux regulator is totally disabled. it does not respond to any svid command with address 01h.
ncp6132a, ncp6132b http://onsemi.com 22 if aux rail is disabled, the unused pins? connection should follow the below table: unused pin connection with disabled aux rail pin name connect to csp1a v cc csp2a v cc lga float swa float hga float bsta float vspa gnd vsna gnd diffa float fba compa compa fba trbsta# float or vcc csrefa gnd cscompa cssuma cssuma cscompa droopa cscompa ilima float tsnsa gnd iouta gnd pwma float there are three integrated drivers: hg1/lg1, hg2/lg2 and hga/lga. there are 5 internal pwm signals: pwm1/2/3 from core controller and pwm1a/2a from aux controller. hg1/lg1 is driven by pwm1, hg2/lg2 is driven by pwm2, and hga/lga is driven by pwm1a when aux rail uses one internal driver, driven by pwm3 when core rail uses 3 internal drivers. to drive the external drivers, ncp6132a/ncp6132b has two pwm signal outputs : pwm and pwma, w hose internal connections depend on the phase and driver configuration. for example, pwm can be driven by pwm3 when there is one external driver needed for core rail, or driven by pwm2a when aux rail requires two external drivers. similarly, pwma can be driven either by pwm1a or pwm2a. the detailed phase configuration table is shown below: phase configuration table aux 1 int. + 1 ext. aux 2 ext. aux 1 int. aux 1 ext. aux off core 2 int. + 1 ext. core drivers : hg1/lg1 hg2/lg2 pwm aux drivers : hga/lga pwma no core drivers : hg1/lg1 hg2/lg2 pwm aux drivers : hga/lga no core drivers : hg1/lg1 hg2/lg2 pwm aux drivers : core 3 int. no core drivers : hg1/lg1 hg2/lg2 hga/lga aux drivers : pwma (phase 1) pwm (phase 2) no core drivers : hg1/lg1 hg2/lg2 hga/lga aux drivers : pwma core drivers : hg1/lg1 hg2/lg2 hga/lga aux drivers : core 2 int. core drivers : hg1/lg1 hg2/lg2 aux drivers : hga/lga pwma core drivers : hg1/lg1 hg2/lg2 aux drivers : pwma (phase 1) pwm (phase 2) core drivers : hg1/lg1 hg2/lg2 aux drivers : hga/lga core drivers : hg1/lg1 hg2/lg2 aux drivers : pwma core drivers : hg1/lg1 hg2/lg2 aux drivers : core 1 int. no no core drivers : hg1/lg1 aux drivers : hga/lga core drivers : hg1/lg1 aux drivers : pwma core drivers : hg1/lg1 aux drivers :
ncp6132a, ncp6132b http://onsemi.com 23 phase interleaving when both core and graphic rails are in multiphase user configuration, ncp6132a/ncp6132b uses phase interleaved pwm operation for dual output rails, i.e., there?s a phase shift between the two rails. the phase shift between core rail and aux rail is to ensure pwm on ? cycle of each interleaved phase has no overlap. it helps reduce the rms current of the input capacitor connected to vin and therefore lower power dissipation over capacitor esr. the interleaved phase angle for different phase configurations is shown in the following diagram. 3+2 core phase 1 0 ? aux phase 1 90 ? aux phase 2 270 ? core phase 2 120 ? core phase 3 240 ? 2+2 core phase 1 0 ? aux phase 1 90 ? aux phase 2 270 ? core phase 2 180 ? figure 7. interleaved phases diagram phase shedding (ps) the ncp6132a/ncp6132b supports phase shedding based by cpu/gpu psx states. (auto phase shedding triggered by user ? set phase shedding threshold without any ps state transition is not supported.) the ncp6132a/ ncp6132b implements ps0, ps1, ps2 and ps3 power saving states for cpu/gpu shown as follows: for cpu (3 ? phase or 2 ? phase user configuration): power status phases operating mode control method ps0 heavy load condition multi ? phase interleaving cf depwm ps1 medium load condition single ? phase forced ccm mode qcf rpm ps2/3 light load condition single ? phase automatic ccm/dcm mode vf rpm for gpu (2 ? phase user configuration): power status phases operating mode control method ps0 heavy load condition 2 ? phase interleaving cf depwm ps1 medium load condition 2 ? phase interleaving cf depwm ps2/3 light load condition single ? phase automatic ccm/dcm mode vf rpm for cpu & gpu (1 ? phase user configuration): power status phases operating mode control method ps0 heavy load condition single ? phase forced ccm mode qcf rpm ps1 medium load condition single ? phase forced ccm mode qcf rpm ps2/3 light load condition single ? phase automatic ccm/dcm mode vf rpm *cf ? constant frequency depwm ? dual edge pulse width modulation qcf ? quasi constant frequency rpm ? ramp pulse modulation vf ? variable frequency
ncp6132a, ncp6132b http://onsemi.com 24 in ps2/3 state, transition from ccm to dcm is triggered by a zero current detector (zcd) latch. zcd latch is set by a zcd comparator monitoring switch node (swn) voltage during pwm off ? time. zcd latch is reset at negative edge of pwm signal and is ready to be set after a set minimum pwm off ? time delay. as swn voltage is stably ramping up toward zero, if the swn voltage crosses a set (a few negative mv) threshold, then zcd latch is set and lg1 output is driven to logic low to turn off low ? side power switch and phase is operating in dcm. if zcd latch remains reset during pwm off ? cycle, then the low ? side power switch remains turned on and the phase is operating in ccm. if aux phase 1 is configured with external driver, the driver should have built ? in zcd comparator (like ncp5911) to support dcm. transition from ps1 to ps0 state triggering phase shedding is called ps1 assertion. similarly, ps2 assertion is the transition to ps2 state. note that ps1 assertion in aux rail should be ignored as ps1 and ps0 have the same phase operating mode. ps1 or ps2 assertion is ignored and user ? set multiphase operation is enforced for the following circumstances: during startup, in current limit (climx) operation, and during dvid transition. phase shedding is always from multiphase to single phase in one single step. ? for core rail: ? phase shedding from 3 ? phase is done by driving pwm output (internally connected to pwm3) to mid ? level while drven output is still driven to logic high, and by keeping both hg2, lg2 outputs to logic low. ? phase shedding from 2 ? phase is done by driving both hg2, lg2 outputs to logic low. ? for aux rail: ? phase shedding from 2 ? phase is done by driving both hga, lga outputs to logic low. transition from ps1/2/3 to ps0 state triggers phase un ? shedding. phase un ? shedding is instantaneous and happens from single ? phase to user ? set multiphase configuration in one single step. serial vid the ncp6132a/ncp6132b supports the intel serial vid interface. it communicates with the microprocessor through three wires (sclk, sdio, alert#). the table of supported registers is shown below. index name description access default 00h vendor id uniquely identifies the vr vendor. the vendor id assigned by intel to on semiconductor is 0x1ah r 0x1ah 01h product id uniquely identifies the vr product. the vr vendor assigns this number. r 0x00 02h product revision uniquely identifies the revision or stepping of the vr control ic. the vr vendor assigns this data. r 0x03 05h protocol id identifies the svid protocol the ncp6132a/ncp6132b supports r 0x01 06h capability informs the master of the ncp6132a/ncp6132b?s capabilities, 1 = supported, 0 = not supported bit 7 = iout_format. bit 7 = 0 when 1a = 1lsb of reg 15h. bit 7 = 1 when reg 15 ffh = icc_max. default = 1 bit 6 = adc measurement of temp supported = 1 bit 5 = adc measurement of pin supported = 0 bit 4 = adc measurement of v in supported = 0 bit 3 = adc measurement of i in supported = 0 bit 2 = adc measurement of p out supported = 1 bit 1 = adc measurement of v out supported = 1 bit 0 = adc measurement of i out supported = 1 r 0xc7 10h status_1 data register read after the alert# signal is asserted. conveying the status of the vr. r 00h 11h status_2 data register showing optional status_2 data. r 00h 12h temp zone data register showing temperature zones the system is operating in r 00h 15h i_out 8 bit binary word adc of current. this register reads 0xff when the iout(a) pin voltage is 2 v. the iout(a) voltage should be scaled with an external resister to ground such that a load equal to icc_max generates a 2 v signal. r 01h 16h v_out 8 bit binary word adc of output voltage, measured between vsp and vsn. lsb size is 8 mv r 01h 17h vr_temp 8 bit binary word adc of voltage. binary format in deg c, ie 100c = 64h. a value of 00h indicates this function is not supported r 01h
ncp6132a, ncp6132b http://onsemi.com 25 index default access description name 18h p_out 8 bit binary word representative of output power. the output voltage is multiplied by the output current value and the result is stored in this register. a value of 00h indicates this function is not supported r 01h 1ch status 2 last read when the status 2 register is read its contents are copied into this register. the format is the same as the status 2 register. r 00h 21h icc_max data register containing the icc_max the platform supports. the value is measured on the iccmax pin on power up and placed in this register. from that point on the register is read only. r 00h 22h temp_max data register containing the max temperature the platform supports and the level vr_hot asserts. this value defaults to 100 c and programmable over the svid interface r/w 64h 24h sr_fast slew rate for setvid_fast commands. binary format in mv/ s. r 0ah 25h sr_slow slew rate for setvid_slow commands. it is 4x slower than the sr_fast rate. binary format in mv/ s r 02h 26h vboot the ncp6132a/ncp6132b will ramp to vboot and hold at vboot until it receives a new svid setvid command to move to a different voltage. default value = 0 v. r 00h 30h vout_max programmed by master and sets the maximum vid the vr will support. if a higher vid code is received, the vr should respond with ?not supported? acknowledge. vr 12 vid format. rw fbh 31h vid setting data register containing currently programmed vid voltage. vid data format. rw 00h 32h pwr state register containing the current programmed power state. rw 00h 33h offset sets offset in vid steps added to the vid setting for voltage margining. bit 7 is sign bit, 0 = positive margin, 1 = negative margin. remaining 7 bits are # vid steps for margin 2s complement. 00h = no margin 01h = +1 vid step 02h = +2 vid steps ffh = ? 1 vid step feh = ? 2 vid steps. rw 00h 34h multivr config for ncp6132a/ncp6132b, vid code change is supported by svid interface with three options as below: option svid command code feature register address (indicating the slew rate of vid code change) setvid_fast 01h >10 mv/ s vid code change slew rate 24h setvid_slow 02h =1/4 of setvid_fast vid code change slew rate 25h setvid_decay 03h no slew rate control, vid code down n/a boot voltage programming the ncp6132a/ncp6132b has a vboot voltage register that can be externally programmed for both core and aux boot ? up output voltage. the vboot voltage can be programmed with a resistor from vboot pin to gnd, or it can be set to 1.1 v by connecting vboot pin to gnd to facilitate mass production. see the boot voltage table. boot voltage table boot voltage (v) resistor value ( ) 0 10k 0.9 20k 1.0 30k 1.1 40k or connect vboot pin to gnd 1.2 50k 1.35 60k or connect vboot pin to v cc
ncp6132a, ncp6132b http://onsemi.com 26 svid addressing the ncp6132a/ncp6132b has fixed svid device addresses for core and aux rail. the core rail address is 0000, and aux rail address is 0001. remote sense amplifier a high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the remote sense amplifier takes the difference of the output voltage with the dac voltage and adds the droop voltage to v diff v vsp v vsn 1.3 v v dac (eq. 1) v droop v csref this signal then goes through a standard error compensation network and into the inverting input of the error amplifier. the non ? inverting input of the error amplifier is connected to the same 1.3 v reference used for the differential sense amplifier output bias. high performance voltage error amplifier a high performance error amplifier is provided for high bandwidth transient performance. a standard type 3 compensation circuit is normally used to compensate the system. differential current feedback amplifiers each phase has a low of fset differential amplifier to sense that phase current for current balance and per phase ocp protection during soft ? start. the inputs to the csref and cspx pins are high impedance inputs. it is recommended that any external filter resistor rcsn not exceed 10 k to avoid offset issues with leakage current. it is also recommended that the voltage sense element be no less than 0.5 m for accurate current balance. fine tuning of this time constant is generally not required. ccsn rcsn dcr lphase 12 swnx vout cspx csref r csn l phase c csn *dcr figure 8. the individual phase current is summed into to the pwm comparator feedback in this way current is balanced is via a current mode control approach. total current sense amplifier the ncp6132a/ncp6132b uses a patented approach to sum the phase currents into a single temperature compensated total current signal. this signal is then used to generate the o utput voltage droop, total current limit, and the output current monitoring functions. the total current signal is floating with respect to csref. the current signal is the difference between cscomp and csref. the ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. the amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (dcr). rth is placed near an inductor to sense the temperature of the inductor. this allows the filter time constant and gain to be a function of the rth ntc resistor and compensate for the change in the dcr with temperature. figure 9. - + csn1 csn2 csn3 swn1 swn2 swn3 1n cref csref cssum cscomp rref1 rref2 rref3 rph1 rph2 rph3 ccs1 ccs2 rth rcs1 rcs2 the dc gain equation for the current sensing: v cscomp ? csref rcs2 rcs1*rth rcs1 rth rph (eq. 2) * iout total * dcr set the gain by adjusting the value of the rph resistors. the dc gain should set to the output voltage droop. if the voltage from cscomp to csref is less than 100 mv at iccmax then it is recommended to increase the gain of the cscomp amp and add a resister divider to the droop pin filter. this is required to provide a good current signal to offset voltage ratio for the ilim pin. when no droop is needed, the gain of the amplifier should be set to provide ~100 mv across the current limit programming resistor at full load. the values of rcs1 and rcs2 are set based on the 220k ntc and the temperature effect of the inductor and should not need to be changed. the ntc should be placed near the closest inductor. the output voltage droop should be set with the droop filter divider. the pole frequency in the cscomp filter should be set equal to the zero from the output inductor. this allows the circuit to recover the inductor dcr voltage drop current
ncp6132a, ncp6132b http://onsemi.com 27 signal. ccs1 and ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. it is best to fine tune this filter during transient testing. f z dcr@25 c 2*pi*l phase (eq. 3) f p 1 2 * pi * rcs2 rcs1*rth@25 c rcs1 rth@25 c * ( ccs1 ccs2 ) (eq. 4) programming the current limit the current ? limit thresholds are programmed with a resistor between the ilim and cscomp pins. the ilim pin mirrors the voltage at the csref pin and mirrors the sink current internally to iout (reduced by the iout current gain) and the current limit comparators. set the value of the current limit resistor based on the user ? set output current limit iout limit or csref ? cscomp voltage at iout limit condition as shown below: r ilim rcs2 rcs1*rth rcs1 rth rph * iout limit *dcr 10 a (eq. 5) or r ilim v csref ? cscomp@ilimit 10 a (eq. 6) programming droop and dac feed ? forward filter the signals droop and csref are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. the total current feedback should be filtered before it is applied to the droop pin. this filter impedance provides dac feed ? forward during dynamic vid changes. programming this filter can be made simpler if cscomp ? csref is equal to the droop voltage. rdroop sets the gain of the dac feed ? forward and cdroop provides the time constant to cancel the time constant of the system per the following equations. cout is the total output capacitance and rout is the output impedance of the system. + ? 5 7 6 csref cscomp cssum cdroop rdroop droop rdroop cout * rout * 453.6x10 6 cdroop rout * cout rdroop figure 10. if the droop at maximum load is less than 100 mv at iccmax we recommend altering this filter into a voltage divider such that a larger signal can be provided to the ilim resistor by increasing the cscomp amp gain for better current monitor accuracy. the droop pin divider gain should be set to provide a voltage from droop to csref equal to the amount of voltage droop desired in the output. a current is applied to the droop pin during dynamic vid. in this case rdroop1 in parallel with rdroop2 should be equal to rdroop. + ? 5 7 6 csref cssum cscomp cdroop rdroop1 droop rdroop2 figure 11. programming iout the iout pin sources a current equal to the ilim sink current gained by the iout current gain. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull ? up resistor from 5 v v cc can be used to offset the iout signal positive if needed. r iout 2.0 v * r limit 10 * rcs2 rcs1*rth rcs1 rth rph * iout icc_max *dcr (eq. 7) programming icc_max and icc_maxa the svid interface provides the platform icc_max value at register 21h for both the core and the aux rails. a resistor to ground on the pwm and pwma pins program these registers at the time the part in enabled. 10 a is sourced from these pins to generate a voltage on the program resistor. the value of the register is 1 a per lsb and is set by the equation below. the resistor value should be no less than 10 k. icc_max 21h r*10 a * 256 a 2v (eq. 8) programming tsns and tsnsa two temperature sense inputs are provided. a precision current is sourced out the output of the tsns and tsnsa pins to generate a voltage on the temperature sense network. the voltages on the temperature sense inputs are sampled by
ncp6132a, ncp6132b http://onsemi.com 28 the internal a/d converter and then digitally converted to temperature and stored in svid register 17h. a 100 k ntc should be used. the rcomp1 and rcomp2 vary with ntc?s temperature characteristics. rcomp2 8.25k rntc 100k cfilter 0.1 f agnd agnd rcomp1 0.0 tsns figure 12. precision oscillator a programmable precision oscillator is provided. the clock oscillator serves as the master clock to the ramp generator circuit. this oscillator is programmed by a resistor to ground on the rosc pin. the rosc pin provides approximately 2 v out and the source current is mirrored into the internal ramp oscillator. the oscillator generates triangle ramps that are 0.5 ~ 2.5 v in amplitude depending on the vrmp pin voltage to provide input voltage feed forward compensation. the oscillator frequency is approximately proportional to the current flowing in the rosc resistor. f osc 1 2 v osc v ref r osc c osc 2t d (eq. 9) where f osc pwm master oscillator frequency v osc oscillator ramp peak ? to ? peak voltage (1 v) v ref rosc pin reference voltage (2 v) r osc rosc pin frequency setting resistor c osc oscillator timing capacitor (2.5 pf) td oscillator loop delay (10 ns) and the per phase switching frequency f sw is given by f sw f osc 12 (eq. 10) the switching frequency range is between 200 khz/phase to 800 khz/phase. programming the ramp feed ? forward circuit the ramp generator circuit provides the ramp used by the pwm comparators. the ramp generator provides voltage feed ? forward control by varying the ramp magnitude with respect to the vrmp pin voltage. the vrmp pin also has a 4 v uvlo function. the vrmp uvlo is only active after the controller is enabled. the vrmp pin is a high impedance input when the controller is disabled. the pwm ramp time is changed according to the following, v ramppk pk pp 0.1 * v vrmp (eq. 11) vin comp ? il duty vramp_pp figure 13. programming trbst# the trbst# pin provides a signal to offset the output after load release overshoot. this network should be fine tuned during the board tuning process and is only necessary in systems with significant load release overshoot. the trbst# network allows maximum boost for low frequency load release events to minimize load release ringing back undershoot. the network time constants are set up to provide a trbst# roll of at higher frequencies where it is not needed. cboost1*rbst1 controls the time constant of the load release boost. this should be set to counter the under shoot after load release. rbst1 + rbst2 controls the maximum amount of boost during rapid step loading. rbst2 is generally much larger then rbst1. the cboost2 * rbst2 time constant controls the roll off frequency of the trbst# function. rbst2 cboost1 rbst1 cboost2 rbst3 fb trbst figure 14. pwm comparators during steady state operation, the duty cycle is centered on the valley of the triangle ramp waveform and both edges of the pwm signal are modulated. during a transient event the duty will increase rapidly and proportionally turning on all phases as the error amp signal increases with respect to the ramps to provide a highly linear and proportional response to the step load.
ncp6132a, ncp6132b http://onsemi.com 29 protection features input under voltage protection ncp6132a/ncp6132b monitors the 5 v vcc supply and the vrmp pin for under voltage protection. the gate driver monitors both the gate driver vcc and the bst voltage. when the voltage on the gate driver is insufficient it will pull hg1, hg2, hga, lg1, lg2, lga, drven low and notify the controller the power is not ready. the gate driver will hold hg1, hg2, hga, lg1, lg2, lga, drven low for a minimum period of time to allow the controller to restart its startup sequence. in this case the pwm and pwma are set back to the mid state and soft start would begin again. see the figure below. dac gate driver pulls drven low during driver uvlo and calibration if drven is pulled low the controller will hold off its startup figure 15. gate driver uvlo restart soft start soft start is implemented internally. a digital counter steps the dac up from zero to the tar get voltage based on the predetermined slew rate in the spec table. the pwm signals will start out open with a test current to collect data on imax/imaxa and for setting internal registers. after the imax/imaxa configuration data is collected the controller enables and sets the pwm signal to the 2.0 v mid state to indicate that the drivers should be in diode mode. drvon will then be asserted and the comp pin released to begin soft ? start. the dac will ramp from zero to the target dac codes and the pwm outputs will begin to fire. each phase will move out of the mid state when the first pwm pulse is produced preventing the discharge of a pre ? charged output. figure 16. soft ? start sequence over current latch ? off protection the ncp6132a/ncp6132b provides two different types of current limit protection. during normal operation a programmable total current limit is provided that scales with the phase count during power saving operation. a second fixed per ? phase current limit is provided for vid lower than 0.25 v, such as during soft ? start. the level of total current limit is set with the resistor from the ilim pin to cscomp pin. internally the current through ilim pin is scaled and then compared to two current thresholds 10 a and 15 a, where 10 a threshold is scaled to indicate the 100% current limit and 15 a indicates the 150% current limit. if 100% current limit is exceeded, an internal latch ? off counter starts. the controller shuts down if the over current fault is not removed after 50 s. if 150% current limit is exceeded, the controller shuts down immediately. to recover from an ocp fault the en pin must be cycled low. the current limit is scaled down along with the phase shedding. phase shedding from 3 ? phase to single phase scales the current limit to its 1/3; phase shedding from 2 ? phase to single phase scales the current limit to its half. for example, for a 3 ? phase design in ps0 state the 100% current limit trips if ilim current exceeds 10 a, but in ps1/2/3 state (phase shedding to single phase) ilim current above 3.3 a will trigger the 100% current limit. under voltage monitor the output voltage is monitored at the output of the differential amplifier for uvlo. if the output falls more than 300 mv below the dac ? droop voltage the uvlo comparator will trip sending the vrdy/vrdya signal low.
ncp6132a, ncp6132b http://onsemi.com 30 over voltage protection during normal operation the output voltage is monitored at the dif ferential inputs vsp and vsn. if the output voltage exceeds the dac voltage by approximately 250 mv, lgx from integrated drivers will be forced high and pwm/pwma will be forced low when ovp is triggered. and then the dac will ramp down to zero to avoid a negative output voltage spike during shutdown. when the dac gets to zero, lgx will be forced high and pwm/pwma will be forced low with drven remaining high. to reset the part the en pin must be cycled low. during soft ? start & dvid, the ovp has a fix threshold at 1.75 v. figure 17. ovp threshold behavior dac vsp_vsn ovp threshold latch off ovp triggered pwm layout notes the ncp6132a/ncp6132b has differential voltage and current monitoring. this improves signal integrity and reduces noise issues related to layout for easy design use. to insure proper function there are some general rules to follow: careful layout in per phase and total current sensing are critical for jitter minimization, accurate current balancing and ilim and iout monitoring. give the first priority in component placement and trace routing to per phase and total current sensing circuit. the per phase inductor current sense rc filters should always be placed as close to the csref and csp pins on the controller as possible. the filter cap from cscomp to csref should also be close to the controller. the temperature ? compensate resistor r th should be placed as close as possible to the phase 1 inductor. the wiring path between r csx and r phx should be kept as short as possible and well away from switch node lines. the refx resistors (10 ) connected to csref pin should be placed near the inductors to reduce the length of traces. the resistors r phx are better to have 0603 package. the above layout notes are shown in figure 18. place the v cc decoupling caps as close as possible to the controller vcc pin. for any rc filter on the vcc and vddbp pins, the resistor should be no higher than 2.2 to prevent large voltage drop. the small high feed back cap from comp to fb should be as close to the controller as possible. keep the fb traces short to minimize their capacitance to ground. cscomp cssum csref + ? c cs1 r cs1 r cs2 r th place as close as possible to nearest inductor r ph1 r ph2 to switch nodes keep this path as short as possible and well away from switch node lines c cs2 + ? + ? csp1 csp2 r ref1 r ref2 to v sense out r csn1 r csn2 c csn1 c csn2 to switch nodes per phase current sense rc should be placed close to cspx pins refx resistors could be placed near the inductors to reduce the number of long traces figure 18.
ncp6132a, ncp6132b http://onsemi.com 31 package dimensions qfn60 7x7, 0.4p case 485bb ? 01 issue a note 3 seating plane k 0.10 c (a3) a a1 d2 b 1 30 31 60 46 e2 60x 15 45 l 60x bottom view top view side view 0.10 c d a b e pin 1 location 0.08 c 0.05 c e 0.07 c 0.05 c a b c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to the plated terminal and is measured abetween 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 7.00 bsc d2 5.50 5.70 e 7.00 bsc e2 5.50 5.70 e 0.40 bsc k l 0.30 0.50 note 4 dimensions: millimeters 0.40 pitch 5.74 0.25 60x 7.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 detail a 2x 2x 0.63 60x l1 detail a l alternate terminal constructions l ?? ?? ??? 0.15 0.30 ref recommended detail c alternate corner lead construction l3 l3 detail c l3 0.10 ref on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp6132a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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